Here is a picture taken at WIRA of a 0-silicon Rainier wafer. The left-most chiplet in the middle is an 8-qubit unit cell break-out. The chiplet to the right of this is a 2×2 array of unit cells (32 qubits). The chiplet to the right of that is a 4×4 array of unit cells (128 qubits). Each wafer contains several hundred of each. There are several more layers of metal that are added after this step that cover up the underlying circuitry, making an optical photo at this stage more interesting than at later stages where it’s like taking a picture of a mirror. At WIRA you can see a lot of cool stuff. Most of what you’re looking at here is the digital SFQ circuitry used to program a problem instance.
cool, thanks for sharing
Technology is pretty sometimes. Very cool.
Well you guys are wonderful. Never I thought I would see a quantum chip by 2008. You have exceeded all expectations!
That is just absolutely delicious; 128 qubits look seriously sexy in the flesh (glass?) I’m sensing a new desktop wallpaper. It would be neat to have a blog post on the aux SFQ stuff too at some point
Usman: Getting this (or one of its descendants) to work properly is a lot harder than just building the circuits… we’re not quite there yet, but I think it is just a matter of time now.
Suz: Yes the image here turned out really nice. We are taking these pictures with a cheap digital camera, we’re thinking of possibly getting some more professional shots done. I will see if I can do a post on the SFQ programmable control circuitry, it is itself extremely interesting…
What are the dimensions of the unit cell?
Ash: about 0.5 x 0.5 mm with the design you’re looking at here. 8×8 = 512 qubits fits in a 5mm square chiplet. It should be possible to shrink this somewhat without any major changes (another factor of 4 in areal density). The programmable control circuitry (SFQ stuff) is designed so that the number of control lines scales logarithmically with device count so we should be able to operate as many devices as we can (a) fit on a chip and (b) yield.
so is your peak density 2048 qubits in a 5mm?
if so what would be the max size of a chipet?
Geordie: actually you are a bit too optimistic
— the unit tile pitch is 700 um, not 500 um — but you are right, there are always ways to shrink it further.
JP: sqrt(2048/8)*0.7mm=11.2 mm on the side. Can realistically grow much larger than that, even without any density improvements (see above) — look up modern die sizes!
Paul B.
Nice post