Some new Rainier science

Here is a short break from the sparse coding mayhem. A recent paper by some interesting folks appeared today on the arxiv. They ran some experiments on the Rainier-based system at USC.

Here is some of what they found:

Our experiments have demonstrated that quantum annealing with more than one hundred qubits takes place in the D-Wave One device… the device has sufficient ground state quantum coherence to realise a quantum annealing of a transverse field Ising model.

Here is a link to the arxiv paper.

Quantum annealing with more than one hundred qubits

“Inside the chip” – new video showing Rainier 128 processor

Here is a video showing how some of the parts of a D-Wave Rainier processor go together to create the fabric of the quantum computer.

The animation shows how the processor is made up of 128 qubits, 352 couplers and nearly 24,000 Josephson junctions. The qubits are arranged in a tiling pattern to allow them to connect to one another.

Enjoy!

Vesuvius: A closer look – 512 qubit processor gallery

The next generation of D-Wave’s technology is called Vesuvius, and it’s going to be a very interesting processor. The testing and development of this new generation of quantum processor is going well. In the meantime, here are some beautiful images of Vesuvius!

Above: An entire wafer of Vesuvius processors after the full fabrication process has completed.

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Above: Photographing the wafer from a different angle allows more of the structure to be seen. Exercise for the reader: Estimate the number of qubits in this image

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Above: A slightly closer view of part of the wafer. The small scale of the structures (<1um) produces a diffraction grating effect (like you see on the underside of a CD) resulting in a beautiful spectrum of colours reflecting from the wafer surface.

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Above: A different angle of shot produces different colours and allows different areas of the circuitry to become visible.

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Above: A close-up image of a single Vesuvius processor on the wafer. The white square seen to the right of the image contains the main ‘fabric’ of 512 connected qubits.

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Above: An image of a processor wire-bonded to the chip carrier, ready to be installed into the computer system. The wires carry the signals to the quantum components and associated circuitry on the chip.

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Above: A larger view of the bonded Vesuvius processor. More of the chip packaging is now also visible in the image.

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Above: The full chip packaging is visible, complete with wafer.

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Quantum processors and ‘co-design’

There is an high-level introductory article written over at physicsandcake explaining how a renewed interest in ‘co-design’ in the field of High Performance Computing relates to D-Wave’s processors and approach to solving problems. Co-design is usually described as the development of software which is designed to exploit features of special purpose hardware, or vice-versa. Here is a link to the post:

Building more intelligent machines: Can ‘co-design’ help?

Enjoy!

Google Tech Talks on D-Wave and Quantum Annealing

Here are two videos about D-Wave and quantum annealing.

This one is me talking about D-Wave and what we do.

This one is Hartmut Neven talking about using our quantum annealing processors for machine learning.

Cool talk on quantum computing and artificial intelligence

This is super excellent. Very nice introduction to quantum computation and superconducting electronics.

Implementation of a Quantum Annealing Algorithm Using a Superconducting Circuit

Implementation of a Quantum Annealing Algorithm Using a Superconducting Circuit

A circuit consisting of a network of coupled compound Josephson junction rf-SQUID flux qubits has been used to implement an adiabatic quantum optimization algorithm. It is shown that detailed knowledge of the magnitude of the persistent current as a function of annealing parameters is key to implementation of the algorithm on this particular type of hardware. Experimental results contrasting two annealing protocols, one with and one without active compensation for the growth of the qubit persistent current during annealing, are presented in order to illustrate this point.

[arxiv:0903.3906]

Multi-qubit synchronization results

Synchronization of Multiple Coupled rf-SQUID Flux Qubits

A practical strategy for synchronizing the properties of compound Josephson junction rf-SQUID qubits on a multiqubit chip has been demonstrated. The impacts of small (~ 1 %) fabrication variations in qubit inductance and critical current can be minimized by the application of a custom tuned flux offset to the CJJ structure of each qubit. This strategy allows for simultaneous synchronization of the qubit persistent current and tunnel splitting over a range of external bias parameters that is relevant for the implementation of an adiabatic quantum processor.

arXiv:0903.1884v1

Short article on D-Wave in New Scientist

A short piece on our current tests on the Rainier chips appeared today in New Scientist. Here it is.

Rainier chips are cooling down

Three Rainier 1st silicon chips are on their way to 10mK. On two of them we are doing  device-level testing, the third has a full 8-qubit unit cell with all the programmable control circuitry bells and whistles… here is the wirebonded chip with the whole Rainier unit cell on it.

For all you many worlds QM types: Kind of cool that this chip may be shared by other universes all doing the same experiments… I have to admit, opening doors between parallel universes is a pretty fun job.