This is the first of a series of technical posts describing aspects of the 128 qubit Rainier processor currently under development at D-Wave. These posts are meant to invite discussion by researchers so fire away if you have questions or think something I’ve posted is wrong or could be explained better.
Where I thought I’d start is by discussing how the interconnection topology, ie. which qubits are connected in hardware, works in the current design. First I’ll start by describing the problem.
An adiabatic quantum computer of the sort we are building is designed to run a class of quantum algorithms called adiabatic quantum algorithms. These algorithms can be used as components of both heuristic and complete solvers. If we focus on running only complete solvers for the moment, the objective of the class of adiabatic quantum algorithms relevant here is to return the global minimum of the function
where are binary (spin) variables, and are real, and is an edge set defining an allowed set of non-zero .
In a real processor design, the edge set will not contain all possible edges. That is, there will be qubits and that are not physically connected in hardware and for all such pairs the coupling term is “hard-coded” to zero. This loss of generality reduces the range of problems that can be solved directly in hardware. Reducing the edge set can even fundamentally change the complexity of the class of problems the hardware can solve. For example, if each qubit can only be connected to a maximum of two other qubits, the problem is tractable classically.
Not only does the number of non-zero connections per qubit matter, the actual pattern of interconnections matters also. One example is that you can draw both planar and non-planar graphs with four connections per qubit, so if for some reason you can only have maximum per qubit connectivity of four it might be better to arrange the interconnect scheme to allow for non-planarity.
In the systems we build, the maximum number of connections per qubit is constrained by noise. In order to couple a qubit into a coupler, the qubit needs a certain amount of inductance. This inductance is obtained by increasing the perimeter of the qubit, which increases the noise seen by the qubit. Increasing the noise a qubit sees has several deleterious effects, all of which I will be discussing in later posts. For now let’s just say that the maximum number is 6 connections per qubit without answering the question of why or how to make it better.
Given 6 connections per qubit, what is the “ideal” layout / interconnect scheme? Answering this depends on what as a designer you are trying to optimize. Let’s say that the primary objective is to make a tile-able unit cell with a maximum of 6 connections per qubit. There are several possible ways to do this. The way we settled on is as follows:
The qubits are topologically loops of niobium. They are interrupted in a variety of places by compound Josephson junctions. Imagine drawing four loops schematically like the outlines of four parallel popsicle sticks lying north-south, and then laying down on top of this the exact same structure rotated by 90 degrees. Each “popsicle stick outline” is a single qubit. The points of intersection are where the coupling devices are placed. This unit cell looks physically like the picture on the left, which is identical to the picture on the right, which is also known as the complete bipartite graph on 4 vertices :
So in this design there are 8 qubits per unit cell, 16 inter-cell couplers per unit cell, and 8 intra-cell couplers (4 to the right, 4 to the bottom). To make the tiling strategy explicit, here are 32-qubit
and 128-qubit interconnect schemes.
The red dots are identical devices to the blue dots, just colored differently to show that they sit between the blocks. This last picture is the interconnect topology / edge set used in the 128-qubit Rainier processor.
So given this edge set we see that the types of problem that can be “natively” solved in this hardware design are as shown in the objective function above, with edge set restricted as shown in this last figure.