We have designed, fabricated and tested an XY addressable readout architecture for superconducting flux qubits in an integrated circuit designed to enable adiabatic quantum optimization algorithms. The readout architecture for an N-qubit system comprises N hysteretic dc SQUIDs and N rf SQUID latches controlled with wires. The latching elements are coupled to the qubits and provide exceptional readout fidelity. The dc SQUIDs are then coupled to the latches to provide coarse readout. A key advantage of this architecture is that the latches are unaffected by the ac currents generated in the dc SQUIDs during switching. We place a lower bound on the readout fidelity of 99.9999% in an 8 qubit test system.